The present invention relates to a method and a system for estimating a plasma damage to a semiconductor device, for example, a gate insulation film, for a layout design of the semiconductor device, and more particularly to a storage medium storing a support program for the layout design.
Semiconductor devices such as microprocessors and semiconductor memories have various active and passive devices and interconnection inter-connecting them which are integrated over a single crystal semiconductor substrate such as a silicon substrate. MOS field effect transistors are often utilized as active devices as being advantageous in realizing the required high integration. The MOS field effect transistor has the following essential structural elements. Source and drain regions are selectively formed in the semiconductor substrate by selective ion-implantation of n-type impurity such as arsenic or p-type impurity such as boron. A channel region is defined between the source and drain regions. A gate insulation film such as silicon dioxide film is formed on the channel region. A gate electrode such as a polysilicon gate electrode is formed on the gate insulation film.
In the manufacturing processes for the semiconductor devices, a dry etching process using a plasma is carried out. For example, the interconnections are formed as follows. An interconnection material such as aluminum is entirely deposited over the semiconductor substrate on which transistors have already been formed. A resist is applied on the interconnection material. An exposure and a development to the resist are then carried out to form a resist pattern on the interconnection material. A plasma etching to the interconnection material is carried out by use of the resist pattern as a mask, thereby forming an interconnection. This plasma etching is advantageous in high etching selectively. This plasma etching is superior for realizing shrinkage of the semiconductor device and increasing the degree of integration of the semiconductor devices.
As the MOS field effect transistor is scaled down, the thickness of the gate insulation film is reduced. It will be considered that an aluminum interconnection is formed which is connected to the gate. Charge of the charge particles of the plasma is supplied through the interconnection to the gate. As a result, a current flows through the gate insulation film, whereby the gate insulation film receives a substantive damage upon the current. Thus causes a drop of yield of the semiconductor device and also a drop in reliability of the semiconductor device. The damage that the gate insulation film receives in the process using the plasma is so called as a plasma damage. The degree of the plasma damage depends upon a size of the interconnection being exposed to the plasma and capturing the charges of the charge particles of the plasma.
FIG. 1 is a fragmentary schematic perspective view illustrative of a semiconductor device to explain a mechanism of causing the plasma damage to the gate insulation film. Field oxide films 3 are selectively formed on a surface of a semiconductor substrate 1 so that an active region 2 is defined by the field oxide film 3. A gate oxide film 4 is formed on the active region 2 of the semiconductor substrate 1. A gate electrode 5 is formed, which extends over the gate oxide film 4 and parts of the field oxide films 3. An inter-layer insulator 6 is entirely formed over the gate electrode 5 and the field oxide film 3. A through hole 7 is formed in the inter-layer insulator 6 and over the gate electrode 5, so that the through hole 7 reaches a part of the top surface of the gate electrode 5.
An aluminum layer is entirely deposited over the inter-layer insulator and also within the through hole 7, so that the aluminum layer within the through hole 7 is in contact with the part of the top surface of the gate electrode 5. A resist is entirely applied on the aluminum layer and then baked. The resist is patterned by a lithography technique to form a resist pattern 9 on the aluminum layer. A plasma etching to the aluminum layer is then carried out by use of the resist pattern 9 as a mask to form an aluminum interconnection 8.
The resist pattern 9 exists over the aluminum interconnection 8. A top surface of the aluminum interconnection 8 is covered by the resist pattern 9 and separated from the plasma, whilst side portions of the aluminum interconnection 8 are exposed to the plasma. Charges of the charge particles of the plasma are captured through the side portions of the aluminum interconnection 8. Namely, the side portions of the aluminum interconnection 8 serve as antenna for capturing the charges of the charge particles of the plasma. The captured charges are supplied through the through hole 7 to the gate electrode 5, whereby the gate electrode 5 is positively charged. As the gate electrode 5 is charged, then a current flows through the gate oxide film 4, whereby the gate oxide film 4 receives the plasma damage. As an area of side walls or side portions of the aluminum interconnection 8 is increased, then the degree of the plasma damage to the gate oxide film 4 is also increased. In general, the degree of the plasma damage to the gate oxide film 4 is approximately proportional to a density of the current.
If the thickens of the aluminum interconnection 8 is fixed, then the amount of the current flowing through the gate oxide film 4 is almost proportional to a length of the circumference of the aluminum interconnection 8, whilst the amount of the current flowing through the gate oxide film 4 is almost inversely proportional to the area of the gate oxide film 4. In prior art, the following antenna ratio xe2x80x9cRxe2x80x9d is used as an index which represents the degree of the plasma damage.
xe2x80x9cRxe2x80x9d=M/S 
where M is the length of the circumference of the aluminum interconnection 8, and S is the area of the gate oxide film 4. The length of the circumference of the aluminum interconnection 8 is almost equal to double of the length of the aluminum interconnection 8.
In consideration of the plasma damage to the gate oxide film 4 due to the charge particles of the plasma, a maximum antenna ratio xe2x80x9cRmaxxe2x80x9d is previously determined as a design rule, wherein the maximum antenna ratio xe2x80x9cRmaxxe2x80x9d corresponds to the highest value of acceptable range of the degree of the plasma damage to the gate oxide film. The layout design for the semiconductor device is carried out so that the antenna ratio xe2x80x9cRxe2x80x9d is not more than the maximum antenna ratio xe2x80x9cRmaxxe2x80x9d.
It is assumed that the interconnection comprises laminations of three layers, for example, a first metal layer M1, a second metal layer M2, and a third metal layer M3. If the plasma etching process is carried out to form each of the first, second, and third metal layers of the interconnection, then the antenna ratio xe2x80x9cRxe2x80x9d of the interconnection corresponds to the sum xcexa3R of individual antenna ratios of the first, second, and third metal layers of the interconnection. In this case, the layout design for the interconnection is carried out so that the sum xcexa3R of individual antenna ratios of the first, second, and third metal layers is not more than the maximum antenna ratio xe2x80x9cRmaxxe2x80x9d.
If the interconnection layer comprises laminations of plural layers, then a contact within the contact hole also comprises the laminations of plural layers. The layout design is carried out so that the total sum of the individual antenna ratios of the plural layers does not exceed the maximum antenna ratio xe2x80x9cRmaxxe2x80x9d. The bottom of the contact within the through hole serves as an antenna. The amount of the current flowing through the gate oxide film 4 is almost proportional to the area of the bottom of the through hole 7 and also almost inversely proportional to the area of the gate oxide film 4. The area of the bottom of the through hole 7 corresponds to the antenna size M so that the antenna ratio xe2x80x9cRxe2x80x9d is calculated.
The above conventional technique is to take a measure to the plasma damage in the processes of layout design. It has also been known that the measure to the plasma damage is taken in the manufacturing processes.
In Japanese laid-open patent publication No. 10-247638, it is disclosed to prevent a plasma damage in aching to a resist pattern with a plasma aching, wherein the resist pattern is to be used as a mask for dry etching to the gate electrode. In this conventional technique, an insulation film is additionally formed on the gate oxide film and a resist pattern is then formed on the insulation film. When the resist pattern is ached by the plasma, then the gate oxide film is covered or protected by the insulation film, whereby the gate electrode is not charged by the plasma. As a result, the plasma damage is prevented.
In Japanese laid-open patent publication No. 10-247638, it is disclosed to prevent a plasma damage in etching to a resist pattern with a plasma etching, wherein the resist pattern is to be used as a mask for dry etching to the gate electrode. In this conventional technique, an insulation film is additionally formed on the gate oxide film and a resist pattern is then formed on the insulation film. When the resist pattern is etched by the plasma, then the gate oxide film is covered or protected by the insulation film, whereby the gate electrode is not charged by the plasma. As a result, the plasma damage is prevented.
In Japanese laid-open patent publication No. 5-30855, it is disclosed to prevent the plasma damage to the gate oxide film in the process of forming the gate electrode. The etching process for etching the gate electrode is carried out by multiple steps of a magnetic field applied high density plasma etching and a magnetic field free high density plasma etching. This conventional technique allows a high speed etching process with preventing the gate electrode from being charged.
The conventional technique described above takes the measure to the plasma damage in the process of layout design. If the interconnection comprises laminations of the three layers, then the total sum of the individual antenna ratios of the individual three layers is calculated, so that the total sum is considered to be the antenna ratio of the interconnection. The individual antenna ratios are independent from the influence of the inter-layers about the plasma damage. For which reason, the plasma damage is not accurately represented by the total sum of the antenna ratios.
For the processes for forming the through hole and the interconnection, the through hole and the interconnection are different in shape, plasma density, and charge-up mechanism. This means that the maximum antenna ratio and the definition of the antenna ratio are different. Accordingly, it seems no sense to simply sum the individual antenna ratios. Even if the individual antenna ratios are simply summed, it seems difficult to accurately estimate the degree oft he plasma damage.
Consequently, in accordance with the conventional layout design method, in case, it not necessarily difficult to accurately estimate the degree of the plasma damage based upon the antenna ratio. The availability of the layout deign in consideration of the degree of the plasma damage is limited.
Meanwhile, the other conventional technique is to take the measure to the plasma damage in the manufacturing processes. This conventional technique increases the manufacturing processes and needs a complicated manufacturing apparatus.
For example, in accordance with the above described conventional technique disclosed in Japanese laid-open patent publication No. 10-247638, the processes for forming the insulation film over the gate oxide film and removal of the insulation film are additionally necessary, thereby increasing the number of the fabrication processes. The side portions of the gate electrode are not covered by the insulation film, for which reason the gate electrode is charged-up by the plasma, whereby the gate insulation film receives the plasma damage.
In accordance with the above described conventional technique disclosed in Japanese laid-open patent publication No. 10-144658, a high frequency voltage generator is additionally necessary for periodically and positively bias the substrate. This means that the manufacturing apparatus is complicated. It is difficult to prevent the gate electrode from being charged up and also prevents the gate oxide film from the plasma damage.
In accordance with the above described conventional technique disclosed in Japanese laid-open patent publication No. 5-308055, the etching processes comprise two processes of the magnetic field applied high density plasma etching process and the magnetic field free high density plasma etching process. In the magnetic field free high density plasma etching process, the etching rate is reduced, whereby the throughput is reduced. In addition, even no magnetic field is applied, then it is difficult to prevent the plasma damage. Other factors than the magnetic field cause the plasma non-uniform which may provides the plasma damage.
In the above circumstances, it had been required to develop a novel method and system for layout design of semiconductor devices free from the above problem.
Accordingly, it is an object of the present invention to provide a novel method for layout design of semiconductor devices free from the above problems.
It is a further object of the present invention to provide a novel method for layout design of semiconductor devices with an accurate estimation on degree of plasma damage to the gate insulation film in plural processes without, however, increasing the manufacturing processes.
It is a still further object of the present invention to provide a novel system for layout design of semiconductor devices with an accurate estimation on degree of plasma damage to the gate insulation film in plural processes without, however, making the manufacturing apparatus complicated.
It is yet a further object of the present invention to provide a novel storage medium which stores a computer program for layout design of semiconductor devices which an accurate estimation on degree of plasma damage to the gate insulation film in plural processes.
The present invention provides a system for estimating a plasma damage for subsequent layout design of a semiconductor device. The system comprises: an antenna ratio extraction unit for extracting an antenna ratio from each of existing provisional layout patterns to be exposed to plasma in each of plasma processes; an index calculation unit connected to the antenna ratio extraction unit for receiving the antenna ratio extracted by the antenna ratio extraction unit and calculating an individual damage index representing a degree of a plasma damage in accordance with the antenna ratio; and an index addition unit damage in accordance calculation unit for receiving the individual damage indexes from the index calculation unit and adding the individual damage indexes to estimate a plasma damage.